1. Field of the Invention
The present invention relates to a sequence controller having a data storing circuit for rewritably storing data such as coil data in byte units and a data processing part for processing the data stored in the byte units.
2. Description of the Related Art
FIGS. 1, 2 and 3 show examples of a conventional sequence controller, respectively.
(1) The sequence controller shown in FIG. 1 includes a CPU (central processing unit) 601, a RAM (random access memory) 602 for storing byte data, a ROM (read only memory) 603 in which control procedures are stored, and an input/output part 604. The CPU 601, the RAM 602, the ROM 603 and the input/output part 604 are connected to one another by a bus 605. Change of bit data at an arbitrary bit in byte data is realized only by software.
(2) The sequence controller shown in FIG. 2 includes a first CPU 701 for handling byte data, a second CPU 702 for handling bit data, a byte-data RAM 703 for storing byte data, a bit-data RAM 704 for storing bit data, a ROM 705 in which control procedures are stored, and an input/output part 706. The first CPU 701, the second CPU 702, the byte-data RAM 703, the bit-data RAM 704, the ROM 705 and the input/output part 706 are connected to one another by a bus 707. To increase the operating speed of the sequence controller, the memory (the bit-data RAM 704) exclusively for storage of bit data and the CPU 702 exclusively for bit operation are provided.
(3) The sequence controller shown in FIG. 3 includes a general-purpose, first CPU 801, a second CPU 802 for executing bit instruction processing for the sequence controller, a RAM 803 for storing byte data, a ROM 804 in which control procedures are stored, and an input/output part 805. The general-purpose, first CPU 801, the second CPU 802, the RAM 803, the ROM 804 and the input/output part 805 are connected to one another by a bus 806. To increase of the operating speed of the sequence controller, the original CPU (the second CPU 802) for executing bit instruction processing for the sequence controller is provided.
However, the above-described conventional arts have the following problems, respectively.
(1) Since change of data at an arbitrary bit in byte data is realized only by software (refer to FIG. 1), several instructions are needed to process one coil instruction and it is, therefore, substantially impossible to increase the operating speed of the sequence controller.
(2) Since the memory (the bit-data RAM 704) exclusively for storage of bit data and the CPU 702 exclusively for bit operation are provided (refer to FIG. 2), the bit-data RAM 704 and the CPU 702 as well as a peripheral circuit for allowing the bus 707 to be shared by the bit-data RAM 704, the CPU 702 and the other elements are needed. This construction leads to an increase in the size of a printed circuit board as well as an increase in cost.
(3) Since the original CPU (the second CPU 802) for executing bit instruction processing for the sequence controller is provided (refer to FIG. 3), a peripheral circuit for allowing the bus 806 to be shared by the other CPU (the first CPU 801) and the CPU (the second CPU 802) for executing bit instruction processing for the sequence controller is needed. This construction leads to increases in development cost and other associated cost